1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device. In particular, the invention relates to a semiconductor integrated circuit device regarding a protective circuit for protecting an element against an abnormal voltage generated in plural power supply systems.
2. Description of Related Art
In recent years, miniaturization and speed-up of a semiconductor integrated circuit have been under way. Along with this, voltage reduction is required of the semiconductor integrated circuit. In parallel therewith, a power supply line is laid out using plural power supply systems for a circuit that is relatively weak against noise in many cases.
For example, in the case where a semiconductor device includes an analog circuit and a digital circuit, the analog circuit is relatively sensitive to a potential change, so the analog circuit and the digital circuit are connected with different power supply systems in many cases.
For the semiconductor integrated circuit including such plural power systems, a protective circuit for protecting a circuit element against breakdown due to a surge voltage, electrostatic electricity, or other such abnormal voltage has been developed. FIG. 20 shows a semiconductor integrated circuit where a protective circuit is provided in plural power supply systems. A power supply line on a low-potential side 903 of a power supply voltage of an analog unit 901 connected with a signal line 909 is connected with a power supply line on a low-potential side 905 of a power supply voltage of a digital unit 902 through a protective circuit 910 as a switching circuit to thereby avoid the breakdown due to the abnormal voltage (see Japanese Unexamined Patent Application Publication No. 9-172146, for example).
In this circuit, if a potential difference between the power supply line on the low-potential side 903 of a power supply voltage of the analog unit 901 and the power supply line on the low-potential side 905 of the power supply voltage of the digital unit 902 exceeds a predetermined level, current flows through the protective circuit 910 to thereby discharge an abnormal current resulting from an abnormal voltage.
Hence, it is possible to avoid such a situation that a potential of the signal line 909 increases along with an increase in potential of the power supply line, and a gate potential of a MOS transistor composing an input circuit 908 is excessively increased to break a gate of the MOS transistor.
However, according to this method, the signal line 909 is protected through a snap-back operation of a MOS parasitic bipolar transistor, so there is a problem in that if the MOS transistor of the input circuit 908 is made up of an ultra-thin film, a gate oxide film is more likely to break before the start of the snap-back operation.
The present inventor has recognized that a clamping voltage for snapback of a transistor (Vclamp) and a breakdown voltage of the gate dielectrics (VBD) are converging in 90 nm process (FIG. 21). In 90 nm process, a region between Vclamp and VBD, called by design window, is narrow.
FIG. 22A shows a general scheme for power protection network and FIG. 22B shows an equivalent circuit of power protection network as shown in FIG. 22A. In a first power supply system 911 having a first circuit 912, a power supply line VDD1 on a high-potential side and a power supply line GND1 on a low-potential side are provided as the power supply lines. In a second power supply system 913 having a second circuit 914, a power supply line VDD2 on a high-potential side and a power supply line GND2 on a low-potential side are provided as the power supply lines.
A signal line 915 is connected between the first circuit 912 and the second circuit 914 to transmit signals between the first circuit 912 and the second circuit 914.
A power supply line protective circuit 916 and a power supply line protective circuit 917 do not operate in normal times but operates when electrostatic electricity, a surge voltage, or other such abnormal voltage is generated. A signal line protective circuit 918 is provided for a protection of the signal line 915.
Vpad is a total stress voltage at a pad, as shown in FIG. 22B, and Vsignal is a stress voltage of the interface gate. The Vpad and Vsignal are described below as an equation.
                              V          pad                =                              V            1                    +                      V            3                    +                                    I              A                        ·                          R              1                                +                                    I                              A                ⁢                                                                                        ·                          R              3                                +                                    I              A                        ·                          R              wire                                                          (        1        )                                          V          signal                =                              V            2                    +                                    (                                                V                  pad                                -                                  V                  2                                            )                        ×                                          R                2                                                              R                  2                                +                                  R                                      _Pch                    ⁢                    _driver                                                                                                          (        2        )            Rwire is described as the representation of wiring resistance along various abnormal current paths. The purpose of the signal line protective circuit 918 is to make the Vsignal smaller than the Vpad. If the Vsignal exceeds the VBD, the gate oxide is broken.
For mixed-power domain protection in narrow design window, a clamping voltage of the back-to-back diodes (=V3; about 1V) has a large dependence on Vpad. Therefore, the signal line protective circuit 918 is necessary for decreasing Vsignal. As the gate oxide thickness of transistor gets thinner, allowed Vsignal becomes smaller and the clamping voltage of the signal line protective circuit 918 (V2) becomes more influential on Vsignal in equation (2).
As described above, in the conventional protective circuit, as the semiconductor circuit becomes smaller and the design window gets smaller, if a clamp voltage after the snap-back operation of the MOS transistor reaches or exceeds a breakdown voltage of the gate oxide film, it is difficult to sufficiently protect a semiconductor device having plural power supply systems against an abnormal voltage on a signal line.